1. Field of the Invention
The present invention relates to multi-level data transfer. More particularly, the present invention relates to a preamplifier circuit and a method of calibrating an offset in a preamplifier circuit.
2. Description of the Related Art
Recently, a parallel transfer mode of input/output data has been replaced with a high-speed serial transfer mode as the operation speed of memory systems has increased. In the parallel transfer mode, a low frequency clock may be used. But the parallel transfer mode has several problems, such as a cost increase due to an increase in the number of required pins, the complexity of routing, the presence of skew and jitter, among other problems. In the serial transfer mode, the cost may be decreased because fewer pins may be required. And the complexity of routing, skew, and jitter may be avoided. A high frequency clock, however, may be required for satisfying a high data transfer rate in the serial transfer mode. Thus, a solution for reducing power consumption and an interface for securing integrity of the transferred signal is needed.
To this end, methods of transferring multi-level input/output data at higher transfer rates have been introduced. One of the methods of transferring multi-level input/output data is pulse amplitude modulation (PAM), such as 2-PAM and 4-PAM. A symbol transfer rate of 4-PAM is a half of a symbol transfer rate of 2-PAM, even though 4-PAM maintains the same data transfer rate of 2-PAM. A receiving stage of 4-PAM requires three reference voltages, whereas a receiving stage of differential 2-PAM is self-referenced.
Generally, a multi-level receiving stage divides the received signal into respective levels using a differential preamplifier. A complementary metal oxide semiconductor (CMOS) differential preamplifier may have offsets resulting from mismatch of circuit constants (e.g., a capacitance and/or a resistance) depending on parameters of operation environments and/or manufacturing processes.
To calibrate a mismatch of a circuit constant, current flowing through an input transistor in the preamplifier may be controlled by adjusting a size of the input transistor. However, an increase in the size of the input transistor, for the purpose of eliminating offsets, can increase a capacitance at an output node. As a result, an output load may also increase, thereby limiting the transfer bandwidth.